USB PHY Debug Register
| OTGIDPIOLOCK | Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value |
| DEBUG_INTERFACE_HOLD | Use holding registers to assist in timing for external UTMI interface. |
| HSTPULLDOWN | Set bit 3 to 1 to pull down 15-KOhm on USB_DP line |
| ENHSTPULLDOWN | Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown |
| RSVD0 | Reserved. |
| TX2RXCOUNT | Delay in between the end of transmit to the beginning of receive |
| ENTX2RXCOUNT | Set this bit to allow a countdown to transition in between TX and RX. |
| RSVD1 | Reserved. |
| SQUELCHRESETCOUNT | Delay in between the detection of squelch to the reset of high-speed RX. |
| RSVD2 | Reserved. |
| ENSQUELCHRESET | Set bit to allow squelch to reset high-speed receive. |
| SQUELCHRESETLENGTH | Duration of RESET in terms of the number of 480-MHz cycles. |
| HOST_RESUME_DEBUG | Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. |
| CLKGATE | Gate Test Clocks |
| RSVD3 | Reserved. |